![]() Entire idea is based on Temporal Locality: if we use it now, we ll want to use it again soon (a Big Idea) Cache Design How do we organize cache? Where does each memory address map to? (Remember that cache is subset of memory, so multiple memory addresses map to the same cache location.) How do we know which elements are in cache? How do we quickly locate them?Ĥ Direct-Mapped Cache (1/2) In a direct-mapped cache, each memory address is associated with one possible block within the cache Therefore, we only need to look in a single location in the cache for the data if it exists in the cache Block is the unit of transfer between cache and memory Direct-Mapped Cache (2/2) Cache Memory Index Memory Address A B C D E F 4 Byte Direct Mapped Cache Cache Location can be occupied by data from: Memory location, 4, 8, 4 blocks => any memory location that is multiple of 4 Issues with Direct-Mapped Tag Index Offset Since multiple memory addresses map to same cache index, how do we tell which one is in there? What if we have a block size > 1 byte? Answer: divide memory address into three fields HEIGHT WIDTH ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to offset if have select within correct block block block Direct-Mapped Cache Terminology All fields are read as unsigned integers. ![]() Memory contains copies of data on disk that are being used. ![]() Cache contains copies of data in memory that are being used. When Processor needs something, bring it into to all higher levels of memory. ![]() S = Static, no need to refresh, ~1ns D = Dynamic, need to refresh, ~ns /paedia/r/ram_guide/ram_ģ Memory Hierarchy Analogy: Library (1/2) You re writing a term paper (Processor) at a table in SEL SEL Library is equivalent to disk essentially limitless capacity very slow to retrieve a book Table is memory smaller capacity: means you must return book when table fills up easier and faster to find a book there once you ve already retrieved it Memory Hierarchy Analogy: Library (2/2) Open books on table are cache smaller capacity: can have very few open books fit on table again, when table fills up, you must close a book much, much faster to retrieve data Illusion created: whole library open on the tabletop Keep as many recently used books open on table as possible since likely to use again Also keep as many books on table as possible, since faster than going to library Memory Hierarchy Basis Disk contains everything. Q: Can $/bit go up as move deeper? Memory Hierarchy (3/3) If level closer to Processor, it must be: smaller faster subset of lower levels (contains most recently used data) Lowest Level (usually disk) contains all available data Other levels? Memory Caching We ve discussed three levels in the hierarchy: processor, memory, disk Mismatch between processor and memory speeds leads us to add a new level: a memory cache Implemented with SRAM technology: faster but more expensive than DRAM memory. Level n Increasing Distance from Proc., Decreasing speed Size of memory at each level As we move to deeper levels the latency goes up and price per bit goes down. Memory Hierarchy (2/3) Processor Higher Levels in memory hierarchy Lower Level 1 Level 2 Level 3. Processor-Memory Performance Gap: (grows 5% / year) 1989 first Intel CPU with cache on chip 1998 Pentium III has two levels of cache on chip DRAM %/yr. Try to keep most of the action in the higher levels.Ģ Performance Review: Why We Use Caches Moore s Law CPU DRAM µproc %/yr. 1 The Big Picture Cache Memory CSE 5.2 Computer Processor Memory (active) (passive) Control (where ( brain ) programs, Datapath data live ( brawn ) when running) Devices Input Output Keyboard, Mouse Disk, Network Display, Printer Slides from Dan Garcia, UCB Memory Hierarchy (1/3) Processor executes instructions on order of nanoseconds to picoseconds holds a small amount of code and data in registers Memory More capacity than registers, still limited Access time ~5-1 ns Disk HUGE capacity (virtually limitless) VERY slow: runs ~milliseconds The Levels in Memory Hierarchy Higher the level, smaller and faster the memory. ![]()
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